As continued semiconductor scaling faces difficulties at device dimensions approaching atomic scale, three-dimensional device integration offers a method of increasing semiconductor devices within a circuit. In three-dimensional integration, a plurality of semiconductor chips is vertically stacked to provide integration of semiconductor devices beyond a single semiconductor chip.
One method of providing electrical connection between vertically adjoined semiconductor chips is “flip chip” technology in which an array of solder balls are employed between two adjoined semiconductor chips that are vertically stacked face to face. However, flip chip technology provides electrical connection between only two vertically stacked semiconductor chip.
Another method of providing electric connection between vertically adjoined semiconductor chips employs an array of conductive vias and an array of conductive sockets. In such schemes, wafers or chips are bonded to other wafers or chips so that each conductive pin on a wafer or a chip matches a conductive socket on another wafer or another chip. The minimum pitch of the conductive pins and the conductive sockets, and hence the density of interconnections between the chips or wafers is determined by the alignment accuracy, or overlay tolerance, of the wafer-to-wafer, chip-to-wafer, or chip-to-chip bonding process.
Referring to FIG. 1, an exemplary prior art semiconductor structure for forming a vertically stacked semiconductor structure is provided. The exemplary prior art semiconductor structure comprises an upper semiconductor structure 110 and a lower semiconductor structure 190 that are aligned to each other, and brought together for bonding. The upper semiconductor structure 110 includes an upper handle substrate 180, an upper semiconductor substrate 170, an array of conductive pins 160, and upper bonding material portions 155. The lower semiconductor structure 190 includes a lower handle substrate 120, a lower semiconductor substrate 130, an array of conductive sockets 140, and lower bonding material portions 145.
The upper semiconductor substrate 170 includes a set of semiconductor devices electrically connected to the array of the conductive pins 160. The lower semiconductor substrate 130 includes semiconductor devices that are electrically connected to the array of the conductive sockets 140. The upper handle substrate 180 and the lower handle substrate 120 are optional, i.e., may, or may not, be present. By bringing the upper semiconductor structure 110 and the lower semiconductor structure 190 together and inducing bonding between the upper bonding material portions 155 and the lower bonding material portions 145, electrical connection is provided between the semiconductor devices in the upper semiconductor substrate 170 and the semiconductor devices in the lower semiconductor substrate 130 through the set of electrical contacts including an array of pairs of a conductive pin 160 and a conductive socket 140. The upper bonding material portions 155 and the lower bonding material portions 145 may comprise dielectric materials, polymers, or metallic materials. There is a one-to-one correspondence between the conductive pins 160 and the conductive sockets 140, i.e., the number of the conductive pins 160 is the same as the number of the conductive sockets 140.
Referring to FIG. 2, the relative portion between a neighboring pair of conductive pins 160 and a matching pair of conductive sockets 140 is schematically illustrated. For the purpose illustration, the conductive pins 160 and the conductive sockets 140 are in perfect lateral alignment. The diameter dp of a conductive pin 160 is typically from about 0.5 micron to about 2 microns. The socket may have a shape of a circle or a regular polygon. The distance between a pair of parallel edges of the regular polygon or the diameter of the circle is herein referred to as a lateral socket dimension LSD, which is limited by overlay tolerance of the bonding process employed to bond the upper semiconductor structure 110 with the lower semiconductor structure 190. Lateral socket dimension LSD may be from about 1 micron to about 10 microns, and is typically from about 3 microns to about 6 microns.
Referring to FIG. 3, the effect of overlay variations during bonding on the size of conductive sockets is shown. To provide effective electrical connection between a conductive pin 160 and a conductive socket 140, the center of the conductive pin 160 must be located within the area of the conductive socket 140 that matches the conductive pin 160. Therefore, the shortest distance between the periphery of the conductive socket 140 and the center of the conductive socket 140 must be at least equal to the overlay tolerance of the bonding process. The circular area within which the center of the conductive pin 160 needs to be placed to provide effective electrical connection between the conductive pin 160 and the conductive socket 140 is herein referred to as a “connectivity alignment field” CAF.
If the radius of the connectivity alignment field CAF is greater than the overlay tolerance of the bonding process, the conductive pin 160 always falls within the area of a matching conductive socket 140. If the radius of the connectivity alignment field CAF is less than the overlay tolerance of the bonding process, electrical contact between the conductive pin 160 and the conductive socket 140 has a statistically significant probability of being inadequate, e.g., the conductive pin 160 and the conductive socket 140 may be electrically disconnected or only insufficiently connected.
Since the conductive pin 160 has a finite area, the area that the conductive pin 160 may occupy at a maximum overlay variation extends beyond the area of the connectivity alignment field CAF by the radius of the conductive pin 160. The area that the conductive pin 160 may possibly cover is herein referred to as an “outermost pin alignment field” OPAF. The outermost pin alignment field OPAF has a radius of the sum of the overlay tolerance of the bonding process and the radius of the conductive pin 160. The pitch of the array of the conductive socket 140 is determined by the constraint that the outermost pin alignment field OPAF of a conductive socket 140 may not touch a neighboring conductive socket 140. Therefore, the minimum pitch of the array of the conductive sockets 160 is the sum of twice the overlay tolerance of the bonding process and the diameter of the conductive pin 160. The pitch of the array of the conductive pins 160 is determined by the pitch of the matching array of conductive sockets 140. For a bonding process having an overlay tolerance of about 3 microns and conductive pins 160 having a diameter dp of about 1 micron, the minimum pitch for the array of conductive sockets 140 and the matching array of conductive pins 160 is about 6.5 microns. The pitch of the array of conductive sockets 140 is limited mostly by the overlay tolerance of the bonding process. As long as the exemplary prior art structure is employed for vertically stacking an upper semiconductor structure and a lower semiconductor structure, the density of interconnects between a wafer-to-wafer, chip-to-wafer, or chip-to-chip bonding process is limited by the minimum pitch of an array of conductive sockets, which is limited by the overlay tolerance of the bonding process.
In view of the above, there exists a need to increase the density of interconnections between wafer-to-wafer, chip-to-wafer, or chip-to-chip bonding processes without being limited by the overlay tolerance of the bonding process.
Particularly, there exists a need for reducing the pitch of interconnections in such vertically bonded structures to a dimension less than the overlay variations in the alignment of an upper semiconductor structure and a lower semiconductor structure.